1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device.
2. Description of the Related Art
Generally, semiconductor memory devices such as a double data rate synchronous dynamic random access memory (DDR SDRAM), have a large number of memory cells. Since the integration degree has increased with the development of process technology, the number of memory cells has further increased. When a fail occurs in any one of the memory cells, a semiconductor memory device having the memory cell must be discarded because the semiconductor memory device cannot perform a desired operation. Recently with the development of the process technology for semiconductor memory devices, a defect occurs only in a small number of memory cells. When a semiconductor memory device is discarded due to such a small number of defects, it is very inefficient in terms of yield. Thus, to solve such a concern, a semiconductor memory device additionally includes redundancy memory cells as well as normal memory cells.
A redundancy memory cell is provided to replace a normal memory cell in which a fail occurred (hereinafter, referred to as a “repair target memory cell”). Specifically, when the repair target memory cell is accessed during a read/write operation, the redundancy memory cell is accessed instead of the repair target memory cell. Thus, when an address corresponding to the repair target memory cell is inputted, the semiconductor memory device performs an operation for accessing the redundancy memory cell instead of the repair target memory cell hereinafter, referred to as a “repair operation”). The repair operation may guarantee a normal operation of the semiconductor memory device.
Generally, a redundancy circuit for the repair operation is provided in each of a plurality of banks included in the semiconductor memory device. The bank includes a cell mat having a plurality of unit cells, a row control region having circuits for controlling a row access, and a column control region having circuits for controlling a column access. The redundancy circuit may include a row redundancy circuit for storing a row address of a unit cell having a defect and a column redundancy circuit for storing a column address of a unit cell having a defect. The row redundancy circuit and the column redundancy circuit are included in the row control region and the column control region of the bank, respectively.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device for describing a repair operation of a row control region.
Referring to FIG. 1, the semiconductor memory device 100 includes a normal mat 110, a repair mat 120, an address latch unit 130, a normal word line selection unit 140, a repair word line selection unit 150, and a mat selection unit 160.
When an active command (not illustrated) is applied to the semiconductor memory device 100, a row address XADD applied from outside is compared with a fail address stored in the address latch unit 130, and a first repair word line select signal XHIT0 is generated when the row address XADD coincides with the fail address. The address latch unit 130 may include a plurality of latches 130_1 to 130_N that may compare the row address XADD with the fail address and generate a plurality of repair word line select signals. The address latch unit 130 may activate a first control signal NXKILL when all of the repair word line select signals are activated. At this tune, the activated first control signal NXKILL is transmitted to the mat selection unit 160 to deactivate a mat select signal MATENB. Thus, in response to the deactivated mat select signal MATENB, the normal word line selection unit 140 does not perform a word line decoding operation for selecting a normal word line within the normal mat 110, and the repair word line selection unit 150 performs a word line decoding operation for selecting a repair word line within the repair mat 120. The first repair word line select signal XHIT0 is transmitted to the mat selection unit 160 and the repair word line selection unit 150. That is, after the first control signal NKKILL which is used to determine whether the row address XADD applied from outside is identical to the fail address or not is generated, the mat selection unit 160 may operate in response to a bank select signal BKSEL. Therefore, tRCD (Row to Column Access Strobe Delay “RAS to CAS Delay”) and tAA (Column Address Access Time) are delayed by a delay time of the first control signal NXKILL and the bank select signal BKSEL.
Although not illustrated, a column control region is configured in a similar manner to the row control region. That is, fail information F_DATA is stored in an address latch unit, and then compared with a column address inputted from outside so as to generate a plurality of signals, and the plurality of signals are used to generate a second control signal. When the column address coincides with the fail information F_DATA, the second control signal does not operate a normal column line selection unit for generating a column select signal. Similar to the row control region, after the second control signal is generated, which is used to determine whether or not the column address is identical to the fail information F_DATA, the mat selection unit may operate in response to a strobe signal. Thus, a delay time of the second control signal and the strobe signal inevitably occurs.
FIG. 2 is a timing diagram describing a repair operation of the conventional semiconductor memory device.
Referring to FIG. 2, when an address A applied after an active command ACT is identical to a fail address, the first control signal NXKILL is generated to determine whether or not a repair operation is required. Then, a repair word line Red.WL is activated in response to the bank select signal BKSEL to be applied afterwards. When an address B applied after a read command RD or write command WT is identical to a fail address, the second control signal NYKILL is generated to determine whether or not a repair operation is required. Then, a repair column select signal Red.YI is activated in response to the strobe signal STROBE to be applied afterwards. Thus, tRCD and tAA are delayed by a delay time t1 between the first control signal NXKILL and the bank select signal BKSEL and a delay time t2 between the second control signal NYKILL and the strobe signal STROBE.